module counter_8bit_demo(
	input Clk_50M,
	input Rst_n,
	output reg Tick,
	output reg[7:0] Count
);

	always @(posedge Clk_50M or negedge Rst_n) begin
		if(Rst_n == 1'b0) begin
			Tick = 1'b0;
			Count = 8'd0;
		end
		else begin
			Tick = ~Tick;
			if(Count == 8'b1111_1111) begin
				Count = 8'd0;
			end
			Count = Count + 1;
		end
	end

endmodule
